Woogeun Rhee is a Professor at Tsinghua University, China. He received the B.S.E.E. degree from Seoul National University in 1991, the M.S.E.E. degree from UCLA, in 1993, and the Ph.D. degree from the University of Illinois, Urbana-Champaign, in 2001. From 1997 to 2001, he was with Conexant Systems, CA, where he was a Principal Engineer and developed low-power low-cost fractional-N synthesizers, e.g. CX74038. From 2001 to 2006, he was with IBM Thomas J. Watson Research Center, NY and worked on clocking area for high-speed I/O serial links. In August 2006, he joined the faculty of Tsinghua University, China. He currently holds 17 U.S. patents. He is a member of the TPC for IEEE ISSCC and A-SSCC conferences. He is an Associate Editor of the IEEE Journal of Solid-State Circuits.

Abstract

A frequency synthesizer is a key building block in wireless systems. The DS PLL based synthesizer plays a critical role in modern transceivers not only as a local oscillator but also as a phase modulator with direct digital modulation. However, the traditional PLL in advanced CMOS technology suffers from poor scalability, loop parameter variability and leakage current problems. Accordingly, diversified PLL architectures and circuit techniques have been recently proposed in consideration of performance, power and cost, thus making it more difficult for circuit designers to choose the right design solution than ever. This tutorial gives some insight into PLL basics tailored for circuit designers. Then, system perspectives and practical circuit design aspects for frequency synthesis will be presented. Furthermore, various PLL architectures and design challenges will be discussed.