Seng-Pan U (Ben) received joint Ph.D. degree from the University of Macau (UM) and the Instituto Superior Técnico (IST), Portugal. He is currently Professor and Deputy Director of State-Key Lab. of Analog & Mixed-Signal VLSI of UM. He is the co-founder of Chipidea Microelectronics (Macau), Ltd. (currently Synopsys Macau Ltd) for analog & mixed-signal IP development and is also Senior Analog Design Manager and Site General Manager. He published 120+ papers and 4 books, and co-hold 7 US patents. As the founding chair, he received the 2012 IEEE SSCS Outstanding Chapter Award. He is also advisor for 20+ student award recipients, incl. ISSCC Silk-Road Award & A-SSCC Student Design Contest for data converter papers. He is currently TPC of A-SSCC, VLSI-DAT, RFIT and Editorial Board member of Springer journal AICSP. .

Abstract

The evolving broadband wireless communication increasingly drives fast development on high-performance consumer portable smart and green gadgets with longer battery life, which leads to growing demands on high-speed ADCs with higher energy efficiency. SAR-type ADCs which take advantages of CMOS technology downscaling for their “highly digital” implementation have been dominating large segments of high-speed and energy efficient ADCs with efficiencies down to fJ/conversion step at 100MHz+ sampling rate. This tutorial provides firstly an overview of the state-of-the-art high energy efficient ADCs, and then discusses the innovative circuit techniques for power, speed and linearity optimizations in SAR ADCs. Next, high-performance SAR-type ADCs, including multi-bit SAR, Binary-Search SAR, Flash SAR and Pipeline SAR, will be investigated with practical design examples from architectural and circuit-level design challenges as well as the calibration techniques for circuit non-idealities.