Supporters & Exhibitors


Important Dates

Aug. 18, 2014
Acceptance notification

Sept. 15, 2014
Deadline for final paper submission
& Author registration deadline


Oct. 31, 2014
Slides due to session chairs

Nov. 9, 2014
Speaker rehearsal

Nov. 10-12, 2014
Conference

Local Time (GMT+8)

Taipei, Taiwan






Speaker Rehearsal

Download: PDF, ZIP


Guidance for A-SSCC2014 Speaker Rehearsal

Venue

National University of Kaohsiung (NUK), 1st General Building, Level 1.

Date

November 9, 2014

Time

13:00 to 18:00


The ASSCC2014 speaker rehearsal is scheduled to from 13:00 to 15:30 and from 15:30 to 18:00 on November 9, 2014 in National University of Kaohsiung (NUK). Please refer to the following sections for more details


Location

Level 1, 1st General Building, National University of Kaohsiung
地址:高雄市楠梓區高雄大學路700號 (See the Map)


Transportation

By Shuttle Bus:
A-SSCC 2014 prepares two shuttle buses for attendants moving in “THSR Zuoying Station NUK” and “85 Sky Tower Hotel NUK”.

Bus Schedule from (THSR Zuoying Station or 85 Sky Tower Hotel) to NUK

Bus Line

Arrival

Departure

Estimated Time to NUK

1. THSR Zuoying Station → NUK

11:50 @ Exit 2, THSR Zuoying Station

12:00 (Depart to NUK)

20 minutes

1. THSR Zuoying Station → NUK

14:20 @ Exit 2, THSR Zuoying Station

14:30 (Depart to NUK)

20 minutes

2. 85 Sky Tower Hotel → NUK

11:50 @ 1F, 85 Sky Tower Hotel

12:00 (Depart to NUK)

40 minutes

2. 85 Sky Tower Hotel → NUK

14:20 @ 1F, 85 Sky Tower Hotel

14:30 (Depart to NUK)

40 minutes

 

Line 1: THSR Zuoying Station → NUK


The Map of THSR Zuoying Station




Line 2: 85 Sky Tower Hotel → NUK





Bus Schedule from NUK to 85 Sky Tower Hotel

Bus Line

Arrival

Departure

Estimated Time

3. NUK → 85 Sky Tower Hotel

15:40 @ 1st General Building

16:00 (Depart to
85 Sky Tower Hotel)

40 minutes

3. NUK → 85 Sky Tower Hotel

15:50 @ 1st General Building

16:10 (Depart to
85 Sky Tower Hotel)

40 minutes

3. NUK → 85 Sky Tower Hotel

18:10 @ 1st General Building

18:30 (Depart to
85 Sky Tower Hotel)

40 minutes

3. NUK → 85 Sky Tower Hotel

18:20 @ 1st General Building

18:40 (Depart to
85 Sky Tower Hotel)

40 minutes

* Speakers can have an advanced registration at 39F, 85 Sky Tower Hotel after 16:10.


Line 3: NUK → 85 Sky Tower Hotel



NUK Campus Map





By Driving:
For the attendants who would like to drive in NUK on November 9, 2014 will need to print and show the gate pass to the guard.
( Download The Gate Pass: PDF, ZIP)



Rehearsal Schedule

Please refer to the following for the rehearsal timing and room location.

Rehearsal Session A

Timing

Session

Session Title

Room

Session Chairs

13:00 – 15:30

02

Communication Systems

102

ShiroDosho, Panasonic, Japan
Hsiang-Hui Chang, Mediatek, Taiwan

04

Energy-efficient Digital Circuits & Systems

101

Keiichi Kushida, Toshiba, Japan
Tai‐Jyi Lin, Chung Cheng University, Taiwan

05

DC-DC Converters

103

Yasuhiro Sugimoto, Chuo University, Japan
Sai‐Weng Sin, University of Macau, Macau

06

High Speed Data Converters

104

Tsung‐Heng Tsai, National Chung‐Cheng University, Taiwan
Takeshi Yoshida, Hiroshima University, Japan

07

Wireline Transceivers

105

Jung‐Hoon Chun, Sungkyunkwan University, Korea
Yoshiyuki Ota, Renesas, Japan

10

Memory Technology

106

Chun Shiah, Etron Technology, Taiwan
Junghwan Choi, Samsung Electronics, Korea

11

Sensor Applications

107

Po‐Chiun Huang, National Tsing Hua University, Taiwan
Seung‐TakRyu, KAIST, Korea

12

mm-wave and THz

108

Minoru Fujishima, Hiroshima University, Japan
Jenny Yi‐Chun Liu, National Tsing Hua University, Taiwan

13

Biomedical Circuits and Systems

109

Jerald Yoo, Masdar Institute of Science and Technology, UAE
Shuenn‐Yuh Lee, National Cheng‐Kung University, Taiwan




Rehearsal Session B

Timing

Session

Session Title

Room

Session Chairs

15:30 – 18:00

03

Industrial Digital Subsystems

102

Daisaburo Takashima, Toshiba, Japan
Ron Ho, Altera, USA

14

SoC and Signal Processing Techniques

101

Kyung Ki Kim, Daegu University, Korea 
An‐Yeu Wu, National Taiwan University, Taiwan

15

Analog Circuits and Systems

103

Tetsuya Hirose, Kobe University, Japan
Li‐Ren Huang, Industrial Technology Research Institute, Taiwan

16

RF Systems

104

Chun HuatHeng, National University of  Singapore, Singapore
Ting‐Ping Liu, Nokia, USA

17

Equalizer and Clock Data Recovery

105

Jun Terada, Nippon Telegraph and Telephone, Japan
Chao‐Cheng Lee, Realtek, Taiwan

18

Circuit Techniques for Emerging Applications

106

Shinichiro Mutoh, Nippon Telegraph and Telephone, Japan
YoungcheolChae, Yonsei University, Korea

19

Low Power ADCs

107

Tai‐Cheng Lee, National Taiwan University, Taiwan
Liyuan Liu, Chinese Academy of Sciences, China

20

RF Building Blocks

108

Baoyong Chi, Tsinghua University, China
Chien‐Nan Kuo, Nationa Chao Tung University, Taiwan

21

High-speed Wireline Building Blocks

109

Bo Zhang, Broadcom, USA
Che‐Fu Liang, Mediatek, Taiwan