Home > Program > Tutorials
[Tutorial 1] Nov. 14 (Mon.), 09:00 – 12:00
Prof. Jri Lee (National Taiwan University, Taiwan)
[Tutorial 2] Nov. 14 (Mon.), 09:00 – 12:00
Dr. Noriyuki Miura (Keio University, Japan)
[Tutorial 3 ]Nov. 14 (Mon.), 13:00 – 16:00
Prof. Byeong-Gyu Nam (Chungnam National University, Korea)
[Tutorial 4] Nov. 14 (Mon.), 13:00 – 16:00
Prof. Zhihua Wang (Tsinghua University, China)

[Tutorial 1] Nov. 14 (Mon.), 09:00 – 12:00

Prof. Jri Lee
National Taiwan University, Taiwan

“Design of Modern CDR Circuits ”


Abstract

Clock and data recovery circuits play essential roles in today’s communication systems. Starting from fundamental phase locking theory, we investigate different CDR approaches such as linear, binary, phase-interpolated, and all digital topologies. System modeling and high-speed circuit techniques are introduced as well. This tutorial also discusses important CDR behaviors, including jitter transfer, jitter tolerance, jitter generation, lock range, etc. Derivative analysis with silicon-proven equations are provided. Several modern CDR design examples are given in the end as a case study.

Biography

Jri Lee received the Ph.D. degree in electrical engineering from the University of California, Los Angeles (UCLA) in 2003. He is currently Professor of electrical engineering in National Taiwan University. Prof. Lee has served as a guest editor of JSSC, and a TPC member in ISSCC, VLSI Symposium, and A-SSCC. He is currently a SSCS distinguished lecturer. He received the Beatrice Winner Award at the 2007 ISSCC, and the Takuo Sugano Award at the 2008 ISSCC. He has published 15 ISSCC papers since 2003.

[Tutorial 2] Nov. 14 (Mon.), 09:00 – 12:00

Dr. Noriyuki Miura
Keio University, Japan

“Non-Contact Interface for 3D Memory System”


Abstract

Three-dimensional (3D) memory stacking is one of the promising approaches to meet increasing demands for memory capacity (especially in NAND Flash), and for memory bandwidth (especially in DRAM). A non-contact interface utilizing inductive coupling, so called ThruChip Interface (TCI), delivers data and clock between stacked memory chips. No additional process steps are needed since existing IC interconnections are used to form metal coils for inductive coupling. In addition, absence of ESD protection results in small channel loading. Therefore, TCI is inexpensive and yet can provide competitive performance compared to TSV. Moreover, the non-contact interface with inductive power delivery opens up new application fields beyond memory stacking, such as a non-contact memory card and a permanent memory system, namely Digital Rosetta Stone. In such applications, another non-contact interface utilizing impedance-matched and therefore wideband Coupled Transmission Lines (CTL) is introduced as a long-distance host interface. This tutorial lecture will cover design fundamentals, key circuit techniques of the non-contact interfaces, and practical and emerging applications in 3D memory system..

Biography

Noriyuki Miura received the B.S., M.S., and Ph.D. degrees in electrical engineering from Keio University, Yokohama, Japan, in 2003, 2005, and 2007 respectively. From 2005 to 2008, he served as a fellow researcher of Japan Society for the Promotion of Science (JSPS). In 2008, he joined Keio University where he is currently working as a research associate at the department of electrical engineering. His current research interest includes interconnect technology for 3D system integration and wireless transceiver circuit design for short-range inter-chip link. Dr. Miura has published more than 50 papers at international conferences and technical journals, and he received 9 technical and academic awards.

[Tutorial 3 ]Nov. 14 (Mon.), 13:00 – 16:00

Prof. Byeong-Gyu Nam
Chungnam National University, Korea

“High-Performance Mobile CPU and GPU Design”


Abstract

Recently, application processors (APs) are widely used in cutting-edge mobile computing devices such as smart phones and smart tablets. In these APs, two major computing units are embedded CPU and GPU cores to schedule system resources and process media rich application workloads. As the mobile applications are getting sophisticated while being battery-powered, high-speed and low-power design of these cores is essential to the success of mobile computing devices. In this talk, high-speed low-power design techniques for mobile CPU and GPU cores will be discussed. It will cover micro-architecture issues, circuit design techniques, technology-level considerations, and power management methodologies.

Biography

Byeong-Gyu Nam received his Ph.D. degree in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2007. His Ph.D. work focused on low-power GPU design for mobile devices. From 2007 to 2010, he was with Samsung Electronics, Giheung, Korea, where he worked on world's first low-power 1-GHz ARM microprocessor design. Dr. Nam is currently with Chungnam National University, Daejeon, Korea, as an assistant professor. His current interests include mobile GPU, embedded microprocessor, low-power SoC design, and their associated software platforms. He is serving as a program committee member of the IEEE ISSCC, A-SSCC, COOL Chips, and VLSI-DAT and a member of IEEE SSCS Seoul Chapter.

[Tutorial 4] Nov. 14 (Mon.), 13:00 – 16:00

Prof. Zhihua Wang
Tsinghua University, China

“CMOS IC Design for Wireless Medical and Health Care ”


Abstract

Wireless medical and health care applications are emerging as one of the major driving forces for today’s semiconductor industry. On the other hand, the advanced CMOS IC technology, as the enabling technology to implement those implantable/portable medical devices, is bringing up a new revolution in the personal medical/healthcare area. In this talk, the system architecture of typical wireless medical and health care applications will be discussed, followed by detailed analysis on the design requirements and challenges. The key design considerations to implement the building blocks of ultra-low power CMOS IC’s for those applications will be examined, including the sensor interface, signal processing, wireless transceivers and embedded controllers. Two design examples will be given to illustrate how those design principles are applied to the ultra-low-power IC’s dedicated for those specific applications.

Biography

Zhihua Wang is a professor at Institute of Microelectronics of Tsinghua Univ., Beijing. His current research mainly focuses on CMOS RFIC and biomedical applications. He has published over 180 papers and 3 books, and holds over 30 patents. Prof. Wang is one of the chief scientists of China Ministry of Science and Technology, and serves on the expert committee of the National High Technology Research and Development Program of China (863 Program) in the area of information science and technologies. He has been a TPC member of ISSCC since 2005. He currently serves as an associate editor for IEEE Transactions on Biomedical Circuits and Systems. Prof. Wang received the B.S., M.S., and Ph.D. degrees in EE from Tsinghua University, Beijing in 1983, 1985 and 1990 respectively.