Tutorials:

Prof. Hyunchol Shin
Kwangwoon University, Seoul, Korea


“Low-Voltage and Low-Power RF Circuits and Transceivers for IoT Applications”

Nov. 9(Mon) 		Xiaoyang ZENG
FUDAN University, Shanghai, China


“high-performance and low power SoC design for information security””

Nov. 9(Mon)
 

   
Ken Takeuchi
Chuo University, Tokyo, Japan


“Dependable Non-volatile Memory System”

Nov. 9(Mon)		 Bo Zhang
Broadcom,USA

“Multi-Gb/s Serial Backplane Transceiver: From Dilemma to Solution”

Nov. 9(Mon)




Title Low-Voltage and Low-Power RF Circuits and Transceivers for IoT Applications
Speaker Prof. Hyunchol Shin
Affiliation Kwangwoon University, Seoul, Korea
Time/Place Track 1: 09:00-10:20Nov. 9 (Mon),2015 / Room #2C
Track 2: 10:40-12:00Nov. 9 (Mon),2015 / Room #2C
Biography:
Hyunchol Shin received the Ph.D. degree in electrical engineering from KAIST, Korea in 1998. After his Ph.D., he had gained professional experience at several institutions and companies, such as Samsung Electronics, Korea, University of California, Los Angeles, CA, Qualcomm, San Diego, CA, all working on RF/analog circuit design for wireless communications. Since 2003, he has been with Kwangwoon University, Seoul, Korea, where he is currently a Professor. From 2010 to 2011, he took a sabbatical leave at Qualcomm Corporate R&D, San Diego, CA. His research focuses on CMOS RF/analog/microwave circuits and PLL frequency synthesizers. Prof. Shin has (co)authored over 70 journal and conference papers and holds 30 patents in the field of RF/analog circuit design. He is a Senior Member of the IEEE, and has served on the technical program committees of several IEEE conferences such as ISSCC, A-SSCC, MWSCAS, RFIT, ISOCC, and IWS.

Abstract:
Short-range wireless connectivity should be an essential and indispensable feature for the emerging IoT devices. For this, low-voltage and low-power operation of RF transceivers are ever more needed. For the ultra-low-voltage and ultra-low-power operation, many traditional RF circuit and transceiver topologies need revisit and rethinking. In this talk, we will discuss the design challenges and recent advances in RF circuits and transceivers to address the emerging market requirements for the IoT’s short-range wireless connectivity applications.



Title high-performance and low power SoC design for information security
Speaker Xiaoyang ZENG
Affiliation FUDAN University, Shanghai, China
Time/Place Track 1: 09:00-10:20Nov. 9 (Mon),2015 / Room #2A02
Track 2: 10:40-12:00Nov. 9 (Mon),2015 / Room #2A02
Biography:
Xiaoyang ZENG received the Ph.D. degree from Chinese Academy of Sciences in China. Since 2001, he joined the State Key Lab of ASIC and System, Fudan University as a post-doctor researcher, where he is currently a full professor and the director. His research interests include information security chip design, VLSI implementation of digital signal processing and communication systems. He has authored over 100 papers on VLSI circuit technology and holds 90 patents. He also serves as the Shanghai chapter chair of IEEE SSCS and a member of the technical program committee of A-SSCC, TPC chair of ASICON 2007/2013, also the international steering committee member of ASP-DAC conferences.

Abstract:
Information Security ICs become more and more important for the data and communication reliability. In this tutorial, the high-performance and low-power SoC design for information security is presented in detail. The tutorial will cover three main topics, one is the SoC platform techniques for information Security, which will include some technologies such as the hardware acceleration of cryptographic algorithms and protocols, embedded single-core and multi-core processors, and power reduction and management techniques. The other is the design technology of security-oriented application specific instruction-set (ASIP), which will include the custom design instructions for multiply security algorithms, also the some novel architectures for ASIP. The last one is the side-channel attacks and its Counter-measures, which will include the circuits design of truly random number generator (TRNG), the model of information leakage from Side-Channels, the circuit logics for anti-power analysis, also the prototype chips with side-channel attacks countermeasures. Some research topics in the future for Information security are also proposed in this tutorials.



Title Dependable Non-volatile Memory System
Speaker Ken Takeuchi
Affiliation Chuo University, Tokyo, Japan
Time/Place Track 1: 13:00-14:20Nov. 9 (Mon),2015 / Room #2C
Track 2: 14:40-16:00Nov. 9 (Mon),2015 / Room #2C
Biography:
Ken Takeuchi is currently a Professor at the Department of Electrical, Electronic, and Communication Engineering of Chuo University. He is now working on the storage system for big-data application, emerging non-volatile memories, 3D-integrated SSDs. Before joining Chuo University, he was an Associate Professor at the University of Tokyo from 2007 till 2012. From 1993 till 2007, he had been leading Toshiba's NAND flash memory circuit design team and commercialized six world's highest density flash memory products. He holds 228 patents worldwide. He won the Takuo Sugano Award for Outstanding Paper at ISSCC 2007. He has served on the program committee of ISSCC, Symposium on VLSI Circuits, A-SSCC, International Memory Workshop, SSDM and NVMTS.

Abstract:
In the Cyber Physical Systems (CPS), huge amount of data are generated by human and sensors. The emerging machine learning algorithms such as the deep learning derive unknown insights based on the data. To best derive an insight, such advanced algorithm need to evaluate a huge volume of data including the not frequently accessed “cold” data or previously exhausted data. As a result, the demand of high capacity nonvolatile memory are increasing.

However, the non-volatile memory has an intrinsic trade-off between the performance and the reliability. If the memory cell is easy to write, it is easy to collapse data. As the memory cell is scaled down and the memory capacity increases , the reliability degradation becomes worse due to process variations, RTN, reduced charge and interference.

This presentation will overview the reliability problems of scaled nonvolatile memories and provide highly reliable circuit and system techniques to achieve the reliability, performance, power and capacity.



Title Multi-Gb/s Serial Backplane Transceiver: From Dilemma to Solution
Speaker Bo Zhang
Affiliation Broadcom, USA
Time/Place Track 1: 13:00-14:20Nov. 9 (Mon),2015 / Room #2A02
Track 2: 14:40-16:00Nov. 9 (Mon),2015 / Room #2A02
Biography:
Bo Zhang received the B.S. and M.S. degrees in EE from Tsinghua University, China, in 1990 and 1992 and the Ph.D. degree in ECE from Oregon State University, USA in 1996.

In 1996, he joined Conexant Systems Inc., Newport Beach, CA, USA, where he was a Principal Engineer. Since late 2000, he has been with Broadcom Corp., Irvine, CA, USA, working on high-speed optical and backplane data transceivers, and he is currently a Senior Technical Director of Central Engineering. His research interests include high-speed analog processing, PLLs, Delta-Sigma modulators and data converters. He invented and co-invented 32 U.S. Patents and published 22 technical papers. He was the recipient of the Broadcom Distinguished Engineer honor in 2009. Since 2013, he has been serving as a TPC member of A-SSCC.

Abstract:
A serial backplane transceiver is referred as a receiver and transmitter with PLL for multi-Gb/s serial digital data communication over circuit boards or cables. It can be found inside racks of service provider’s data centers. This tutorial will start with overview of backplane and its channel impairments such as insertion loss, reflection and crosstalk etc. It is followed by channel equalization choices and tradeoffs for serial backplane transceiver. The latest state-of-the-art low power backplane transceiver architectures and circuit design techniques will be presented. It highlights transmitter with various driver structures and feed-forward equalizer (FFE) and receiver with linear equalizer, variable gain amplifier, adaptive decision feedback equalizer (DFE), including low power design solutions on analog DFE and ADC based DFE.