Program Schedule
Monday, November 12
Mon, Nov 12 | Tue, Nov 13 | Wed, Nov 14
Tutorial
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9:30-12:25 Tutorial I: SoC Power Reduction and Management Techniques Stefan Rusu, Intel |
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9:30-12:25 Tutorial II: Designing CMOS Wireless LAN System-on-a-Chip Srenik Mehta, Qualcomm Atheros |
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13:25-16:20 Tutorial III: High Performance Non-Volatile Memory Design in Nano-Scale Era Dr. Sungdae Choi, SK hynix |
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13:25-16:20 Tutorial IV: Smart Sensor Design in Standard CMOS Kofi Makinwa, Delft University of Technology |
| 16:00-18:30 Student Design Contest Exhibition (Reception Hall) |
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17:30-19:30 A-SSCC 2012 Reception (Reception Hall) Reception (Nov. 12) and Banquet (Nov. 13) are supported by industry supporters. We sincerely thank our industry supporters for A-SSCC 2012. |
Tuesday, Nov 13
Mon, Nov 12 | Tue, Nov 13 | Wed, Nov 14
| 9:00-9:10 Opening Ceremony |
| 9:10-9:20 Welcome Remarks |
Plenary Session 1
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09:20-10:05 Plenary Talk 1: Expectations for the Semiconductor Technologies in EVs and HVs Dr. Shoichi Sasaki, Professor, Keio University, Japan |
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10:05-10:50 Plenary Talk 2: Semiconductor Memory Scaling and Beyond Dr. Sungjoo Hong, Senior VP, Head of R&D Division, SK hynix Inc., Korea, South |
Industry Session 1: Leading Edge SoCs and Memory
Co-Chairs :
Stefan Rusu, Intel Corporation
Shao-Jun Wei, Tsinghua University
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11:05-11:30 The First 22 nm IA System-on-Chip Using tri-Gate Transistors Sanjib Sarkar,Scott Siers, Satish Damaraju, Varghese George, Sanjeev Jahagirdar, Tanveer Khondker, Robert Milstrey, Israel Stolero, Arun Subbiah Intel, United States |
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11:30-11:55 A 1.94mm2, 38.17mW Dual VP8/H.264 Full-HD Encoder/Decoder LSI for Social Network Services (SNS) Over Smart-Phones Chi-Cheng Ju, Tsu-Ming Liu, Yi-Hau Chen, Kun-Bin Lee, Chia-Yun Cheng, Hsueh-Te Chao, Chih-Ming Wang, Tung-Hsing Wu, Tin-An Lin, Han-Liang Chou, Yu-Kun Lin, Cheng-Hung Liu Mediatek, Taiwan |
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11:55-12:20 A High Performance 64Gb MLC NAND Flash Memory in 20nm CMOS Technology Jinsu Park, Sangdon Lee, Kwangho Baek, Chunwoo Jeon, Taikyu Kang, Minsu Kim, Daeil Choi, Jeawon Choi, Hyun Chung, Jongwoo Kim, Eunseong Jang, Changhyuk Lee SK hynix semiconductor, Korea, South |
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12:20-12:45 The Next Generation 64b S3 Core in a SPARC T4 Processor Jinuk Luke Shin, Robert Golla, Hongping Li, Sudesna Dash, Mary Jo Doherty, Greg Grohoski, Curtis McAllister Oracle, United States |
Industry Session 2: Energy Efficient Circuits for Emerging Applications
Co-Chairs :
Ron Ho, Oracle
Koji Kai, Panasonic
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11:05-11:30 0.5V Start-Up 0.77mm2 Dual Drive Mode on-Chip Single-Inductor Dual-Output (SIDO) DC-DC Boost Converter for Battery and Solar Cell Operation Portable Equipments Yasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu Renesas Electronics, Japan |
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11:30-11:55 Circuit Design Challenges and Solutions for Optical Ring Modulators Philip Amberg, Eric Chang, Frankie Liu, Jon Lexau, Xuezhe Zheng, Guoliang Li, Ivan Shubin, John Cunningham, Ashok Krishnamoorthy, Ron Ho Oracle Labs, United States |
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11:55-12:20 A 0.5V 10MHz-to-100MHz 0.47ƒÊW/MHz Power Scalable Ad-PLL in 40nm CMOS Yasuyuki Hiraku{2}, Isamu Hayashi{2}, Hayun Chung{1}, Tadahiro Kuroda{1}, Hiroki Ishikuro{1} {1}Keio University, Japan; {2}Semiconductor Technology Academic Research Center, Japan |
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12:20-12:45 A Low-Power 6.6-Gb/S Wireline Transceiver for Low-Cost FPGAs in 28nm CMOS Jafar Savoj, Kenny Hsieh, Fu-Tai An, Michael Buckley, Jay Im, Xuewen Jiang, Anup Jose, Vassili Kireev, Kang Wei Lai, Hiep Pham, Didem Turker, Daniel Wu, Ken Chang Xilinx, Inc., United States |
Session 1: Analog Interfaces and Amplifiers
Co-Chairs :
Tetsuya Hirose, Kobe University
Seng-Pan U, University of Macau
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13:45-14:10 An Energy-Efficient BBPLL-Based Force-Balanced Wheatstone Bridge Sensor-to-Digital Interface in 130nm CMOS Jelle Van Rethy, Hans Danneels, Valentijn De Smedt, Wim Dehaene, Georges Gielen KU Leuven, Belgium |
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14:10-14:35 An Integrated 12-V Electret Earphone Driver with Symmetric Cockcroft-Walton Pumping Topology for in-Ear Hearing Aids Jen-Huan Tsai{2}, Chun-Yen Tseng{2}, Wei-Kai Tseng{2}, Tim K. Shia{1}, Po-Chiun Huang{2} {1}Industrial Technology Research Institute, Taiwan; {2}National Tsing-Hua University, Taiwan |
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14:35-15:00 A Chopper Stabilized Instrumentation Amplifier with Dual DC Cancellation Servo Loops for Biomedical Applications Dong Han, Yuanjin Zheng Nanyang Technological University, Singapore |
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15:00-15:25 A 0.02mV/C Digital Offset Compensation Technique for Comparators and Differential Amplifiers Koon Lun Jackie Wong, Michael Le, Kwang Young Kim Broadcom, United States |
Session 2 : Advanced Memory
Co-Chairs :
Ken Takeuchi, Chuo University
Meng-Fan Marvin Chang, National Tsing Hua University
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13:45-14:10 Adaptive Program Verify Scheme for Improving NAND Flash Memory Performance and Lifespan Sang In Park{1}, Dongkun Shin{2} {1}Samsung Electronics, Korea, South; {2}Sungkyunkwan University, Korea, South |
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14:10-14:35 An Efficient BCH Decoder with 124-Bit Correctability for Multi-Channel SSD Applications Hung-Yuan Tsai, Chi-Heng Yang, Hsie-Chia Chang National Chiao Tung University, Taiwan |
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14:35-15:00 A 250-MHz 18-Mb Full Ternary Cam with Low Voltage Match Line Sense Amplifier in 65nm CMOS Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, Masaya Shirata, Shizuo Morizane, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai Renesas Electronics, Japan |
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15:00-15:25 An Embedded Energy Monitoring Circuit for a 128kbit SRAM with Body-Biased Sense-Amplifiers Yildiz Sinangil, Anantha P. Chandrakasan Massachusetts Institute of Technology, United States |
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15:25-15:50 A 0.2V 16Kb 9T SRAM with Bitline Leakage Equalization and Cam-Assisted Write Performance Boosting for Improving Energy Efficiency Bo Wang{2}, Truc Quynh Nguyen{2}, Jun Zhou{1}, Minkyu Je{1}, Tony T. Kim{2}, Anh Tuan Do{2} {1}Institute of Microelectronics, Singapore; {2}Nanyang Technological University, Singapore |
Session 3 : TX RX Architecture and Building Blocks
Co-Chairs :
Shuya Kishimoto, NEC
Chun-Huat Heng, National University of Singapore
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13:45-14:10 A Low-power Reconfigurable Multi-Band Sliding-IF Transceiver for WBAN Hubs in 0.18um CMOS Lingwei Zhang, Hanjun Jiang, Jianjun Wei, Jingjing Dong, Weitao Li, Jia Gao, Jianwei Cui, Fule Li, Baoyong Chi, Chun Zhang, Zhihua Wang Tsinghua University, China |
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14:10-14:35 A 65nm CMOS, 1.5-mm2 Bluetooth Transceiver with Integrated Antenna Filter for Co-Existence with a WCDMA Transmitter Mitsuyuki Ashida, Hideaki Majima, Yoshiaki Yoshihara, Mai Nozawa, Shoko Oda, Yoshinori Suzuki, Hiroyuki Kobayashi, Jun Deguchi, Shouhei Kousai, Ryuichi Fujimoto, Shinichiro Ishizuka, Shunji Kawaguchi, Yasuo Unekawa, Mototsugu Hamada, Tadashi Terada Toshiba, Japan |
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14:35-15:00 A Power-Efficient All-Digital IR-UWB Transmitter with Configurable Pulse Shaping by Utilizing a Digital Amplitude Modulation Technique Shuli Geng{2}, Xican Chen{2}, Woogeun Rhee{2}, Jongjin Kim{1}, Dongwook Kim{1}, Zhihua Wang{2} {1}Samsung Advanced Institute of Technology, Korea, South; {2}Tsinghua University, China |
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15:00-15:25 A 1.55mW Mixed-Signal Integrating Mixer for Direct Spectrum Estimation in 0.13um CMOS Kevin Banovic, Anthony Chan Carusone University of Toronto, Canada |
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15:25-15:37 A 2.4 GHz CMOS Doherty Power Amplifier with Dynamic Biasing Scheme Kohei Onizuka, Katsuyuki Ikeuchi, Shigehito Saigusa, Shoji Otaka Toshiba, Japan |
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15:37-15:49 A 3.0-W Wireless Power Receiver Circuit with 75-% Overall Efficiency Young-Jin Moon{1}, Yong-Seong Roh{1}, Changsik Yoo{1}, Dong-Zo Kim{2} {1}Hanyang University, Korea, South; {2}Samsung Electronics, Korea, South |
Session 4 : Energy Efficient Circuits and Techniques
Co-Chairs :
Utpal Desai, Intel Corpration
Keiichi Kushida, Toshiba
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13:45-14:10 A Built-in Self-Adjustment Scheme with Adaptive Body Bias Using P/N-Sensitive Digital Monitor Circuits A.K.M Mahfuzul Islam, Kamae Norihiro, Ishihara Tohru, Onodera Hidetoshi Kyoto University, Japan |
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14:10-14:35 Green Semiconductor Technology with Ultra-Low Power on-Chip Charge-Recycling Power Circuit and System Kazuhiro Ueda{2}, Syunsuke Okura{2}, Fukashi Morishita{2}, Kazutami Arimoto{1}, Leona Okamura{3}, Tsutomu Yoshihara{3} {1}Okayama Prefectural University, Japan; {2}Renesas Electronics, Japan; {3}Waseda University, Japan |
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14:35-15:00 On-Chip Dual-Ring-Oscillator-Based Random-Fluctuation-Measurement Method for Detecting Lowest Voltage in Adaptive Voltage Scaling Systems Goichi Ono, Misa Owa, Michiaki Nakayama, Yusuke Kanno Hitachi, Japan |
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15:00-15:25 Monitoring Effective Supply Voltage Within Power Rails of Integrated Circuits Takeshi Okumoto, Kumpei Yoshikawa, Makoto Nagata Kobe University, Japan |
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15:25-15:50 A 0.3-V All Digital Crystal-Less Clock Generator for Energy Harvester Applications Jen-Chieh Liu{1}, Wei-Chun Lee{1}, Hong-Yi Huang{3}, Kuo-Hsing Cheng{2}, Chao-Jen Huang{1}, Yu-Wei Liang{1}, Jia-Hung Peng{1}, Yuan-Hua Chu{1} {1}Industrial Technology Research Institute, {2}National Central University, Taiwan; {3}National Taipei University, Taiwan |
16:05-17:45 Panel Discussion 1: Disruptive Design for Emerging Technology after 3D Devices/FinFET and Beyond; How Can We Make It?
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Organizer: Yung-Chow Peng, TSMC, Taiwan Co-organizer: Youngmin Shin, Samsung, Korea,South Moderator: Toshiro Hiramoto, The University of Tokyo, Japan Panelist: Vinod Kariat, Cadence, United States Seiichiro Yamaguchi , Fujitsu, Japan Aaron Thean, IMEC, Belgium Jae Cheol Son, Samsung, Korea, South Jong-Ho Lee, Seoul National University, Korea, South Philippe Magarshack, STMicroelectronics, France Sally Liu, TSMC, Taiwan |
16:05-17:45 Panel Discussion 2: Challenge for Zero Stand-by Power Management - Road-map to the "Normally-Off Computing"
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Organizer: Kazutami Arimoto, Okayama Prefecture University, Japan Co-organizer: Toru Shimizu, Renesas Electronics, Japan Moderator: Hiroshi Nakamura, The University of Tokyo, Japan Panelist: S. Fujita, Toshiba, Japan: H. J. Yoo, KAIST, Korea, South M. Hayashikoshi, Renesas Electronics, Japan H. Takada, Nagoya University, Japan Steven Bartling, Texas Instruments, United States TBD, IMEC, Belgium Shey-shi, National Taiwan University, Taiwan |
| 18:00 Shuttle bus to banquet (Meet at the conference registration) |
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19:00-21:20 A-SSCC 2012 Banquet (Kobe Dinner Cruising) We sincerely thank our industry supporters for A-SSCC 2012 Reception (Nov. 12) and Banquet (Nov. 13). |
Wednesday, November 14
Mon, Nov 12 | Tue, Nov 13 | Wed, Nov 14
Plenary Session 2
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09:00-09:45 Plenary Talk 3: Integrated Circuits and Systems toward Smart Ubiquitous Patient-Centered Medical Environment Dr. Ming-Fong Chen, Superintendent, NTU Hospital, Taiwan |
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09:45-10:30 Plenary Talk 4: Technology Challenges and Opportunities for Ubiquitous Computing Dr. Shekhar Borkar, Intel Fellow, Intel, United States |
Session 5 : High Speed Transceivers and Building Block
Co-Chairs :
Jun Terada, NTT
Byungsub Kim, Postech
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10:45-11:10 A 20Gb/S Adaptive Duobinary Transceiver Shen-Iuan Liu, I-Ting Lee, Yu-Ming Ying National Taiwan University, Taiwan |
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11:10-11:35 A 2.3-mW, 5-Gb/S Decision-Feedback Equalizing Receiver Front-End with Static-Power-Free Signal Summation and CDR-Based Precursor ISI Reduction Seuk Son, Hanseok Kim, Myeong-Jae Park, Kyunghoon Kim, Jaeha Kim Seoul National University, Korea, South |
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11:35-12:00 A 24-Gb/S Source-Series Terminated Driver with Inductor Peaking in 28-nm CMOS Kosuke Suzuki, Yasumoto Tomita, Hisakatsu Yamaguchi, Tszshing Cheung, Takuji Yamamoto, Hirotaka Tamura Fujitsu Laboratories, Japan |
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12:00-12:25 A 5 Gb/S 1/4-Rate Clock and Data Recovery Circuit Using Dynamic Stepwise Bang-Bang Phase Detector Yen-Long Lee{2}, Soon-Jyh Chang{2}, Rong-Sing Chu{2}, Ying-Zu Lin{2}, Yen-Chi Chen{2}, Jih Ren Goh{2}, Chung-Ming Huang{1} {1}Himax Technologies, Inc., Taiwan; {2}National Cheng-Kung University, Taiwan |
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12:25-12:50 A 0.1-1.5 GHz 8-Bit Inverter-Based Digital-to-Phase Converter Using Harmonic Rejection Ming-Shuan Chen, Amr Amin Hafez, Chih-Kong Ken Yang UCLA, United States |
Session 6: Nyquist-Rate ADCs
Co-Chairs :
Tai-Cheng Lee, National Taiwan University
Soon-Jyh Chang, National Cheng-Kung University
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10:45-11:10 A 1-GHz, 17.5-mW, 8-Bit Subranging ADC Using Offset-Cancelling Charge-Steering Amplifier Kenichi Ohhata, Hiroyuki Takase, Minehiko Tateno, Mai Arita, Naohiro Imakake, Yuutou Yonemitsu Kagoshima University, Japan |
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11:10-11:35 Inter-Stage Gain Error Self-Calibration of a 31.5fJ 10b 470MS/S Pipelined-SAR ADC Zhong Jianyu, Zhu Yan, Sin Sai Weng, U Seng Pan, Martins Rui Paulo Univ. of Macau, China |
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11:35-12:00 A 12-Bit 8.47-fJ/Conversion-Step 1-Ms/S SAR ADC Using Capacitor-Swapping Technique Meng-Hsuan Wu, Yung-Hui Chung, Hung-Sung Li MediaTek, Taiwan |
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12:00-12:25 A 40nm CMOS Full Asynchronous Nano-Watt SAR ADC with 98% Leakage Power Reduction by Boosted Self Power Gating Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro Keio University, Japan |
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12:25-12:37 A 0.05mm^2 0.6V 500kS/S 14.3fJ/Conversion-Step 11-Bit Two-Step Switching SAR ADC for 3-Dimensional Stacking CMOS Imager Jin-Yi Lin{2}, Hsin-Yuan Huang{2}, Chih-Cheng Hsieh{2}, Hung-I Chen{1} {1}Industrial Technology Research Institute, Taiwan; {2}National Tsing Hua University, Taiwan |
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12:37-12:49 A 9b 1GS/S 27mW Two-Stage Pipeline ADC in 45nm SOI-CMOS Jorge Pernillo{1}, Michael Flynn{2} {1}Univeristy of Michigan, United States; {2}University of Michigan, United States |
Session 7 : Emerging Biomedical Circuits and Systems
Co-Chairs :
Reiji Hattori, Kyusyu University
Koji Kotani, Tohoku University
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10:45-11:10 Ultrasonic Imaging Front-End Design for CMUT: a 3-Level 30Vpp Pulse-Shaping Pulser with Improved Efficiency and a Noise-Optimized Receiver Kailiang Chen, Anantha Chandrakasan, Charles Sodini MIT, United States |
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11:10-11:35 A Wirelessly Powered and Interrogated Blood Flow Monitoring Microsystem Fully Integrated with a Prosthetic Vascular Graft for Early Failure Detection Jia Hao Cheong{1}, Chee Keong Ho{1}, Simon Sheung Yan Ng{1}, Rui-Feng Xue{1}, Hyouk-Kyu Cha{2}, Pradeep Basappa Khannur{1}, Xin Liu{1}, Andreas Astuti Lee{1}, Woo-Tae Park{2}, Li Shiah Lim{1}, Cairan He{1}, Minkyu Je{1} {1}Institute of Microelectronics, A-STAR (Agency for Science, Technology and Research), Singapore; {2}Seoul National University of Science and Technology, Korea, South |
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11:35-12:00 An Inductively Powered CMOS Multichannel Bionic Neural Link for Peripheral Nerve Function Restoration Kian Ann Ng{3}, Xu Liu{3}, Jianming Zhao{3}, Shih-Cheng Yen{3}, Yong Ping Xu{3}, Ter Chyan Tan{2}, Minkyu Je{1} {1}Institute of Microelectronic, Singapore; {2}National University Hospital, Singapore; {3}National University of Singapore, Singapore |
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12:00-12:25 100-Channel Wireless Neural Recording System with 54-Mb/S Data Link and 40%-Efficiency Power Link Minkyu Je{1}, Kuang-Wei Cheng{1}, Xiaodan Zou{1}, Jia Hao Cheong{1}, Rui-Feng Xue{1}, Zhiming Chen{1}, Lei Yao{1}, Hyouk-Kyu Cha{1}, San Jeow Cheng{1}, Peng Li{1}, Lei Liu{2}, Luis Andia{1} {1}Institute of Microelectronics, A-STAR (Agency for Science, Technology and Research), Singapore; {2}Nanyang Technological University, Singapore |
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12:25-12:37 A Dynamic Impedance Matched Acupuncture-Type Diagnosis System with Concurrent Feedback of Physiological Signals Kiseok Song, Sunjoo Hong, Taehwan Roh, Unsoo Ha, Hoi-Jun Yoo KAIST, Korea, South |
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12:37-12:49 A Single-Chip Time-Interleaved 32-Channel Analog Beamformer for Ultrasound Medical Imaging Ji-Yong Um, Jae-Hwan Kim, Eun-Woo Song, Yoon-Jee Kim, Jae-Yoon Sim, Hong-June Park POSTECH, Korea, South |
Session 8 : Low-Power Digital Communication and Multimedia SoCs
Co-Chairs :
Hirofumi Sumi, Sony
Donghyun Kim, Samsung Techwin
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10:45-11:10 A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis Chen Yang Lin, Cheng Chi Wong, Hsie Chia Chang National Chiao Tung University, Taiwan |
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11:10-11:35 First (50,2,4) Nonbinary LDPC Convolutional Code Decoder Chip Over GF(256) in 90nm CMOS Chia-Lung Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee National Chiao Tung University, Taiwan |
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11:35-12:00 A Successive Cancellation Decoder ASIC for a 1024-Bit Polar Code in 180nm CMOS Anadi Mishra{3}, Alexandre Raymond{1}, Luca Amaru{3}, Gabi Sarkis{1}, Camille Leroux{2}, Pascal Meinerzhagen{3}, Andreas Burg{3}, Warren Gross{1} {1}McGill University, Montreal, Canada; {2}Institut Polytechnique de Bordeaux, Bordeaux, France; {3}EPFL, Switzerland |
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12:00-12:25 Crisp-II: Coarse-Grained Reconfigurable Image Stream Processor for Image-Processing and Intelligent Operations in QFHD Video Cameras Teng-Yuan Cheng, Liang-Gee Chen, Shao-Yi Chien National Taiwan University, Taiwan |
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12:25-12:37 A Dynamic Resource Controller with Network-on-Chip for a 10.5nJ/Pixel Object Recognition Processor Jinwook Oh, Injoon Hong, Gyeonghoon Kim, Junyoung Park, Hoi-Jun Yoo KAIST, Korea, South |
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12:37-12:49 An 800Mhz Cryptographic Pairing Processor in 65nm CMOS Yang Li, Jun Han, Shuai Wang, Dabing Fang, Xiaoyang Zeng Fudan University, China |
Session 9 : Power Management ICs
Co-Chairs :
Seung-Tak Ryu, KAIST
Po-Chiun Huang, National Tsing Hua University
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13:50-14:15 A Package Bondwire Based 80% Efficiency 80MHz Fully-Integrated Buck Converter with Precise DCM Operation and Enhanced Light-Load Efficiency Cheng Huang, Philip Mok The Hong Kong University of Science and Technology, Hong Kong |
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14:15-14:40 A Single-Inductor Dual-Output (SIDO) Converter with Switchable Digital-or-Analog Low-Dropout Regulator for Ripple Supression and High Efficiency Operation Yu-Huei Lee{1}, Wei-Chung Chen{1}, Chao-Chang Chiu{1}, Kuan-Yu Chu{1}, Ke-Horng Chen{1}, Ying-Hsi Lin{2}, Chen-Chih Huang{2}, Chao-Cheng Lee{2} {1}National Chiao Tung University, Taiwan; {2}Realtek Semiconductor,Taiwan |
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14:40-15:05 Automatic Loading Dectection (ALD) Technique for 92% High Efficiency Interleaving Power Factor Correction (PFC) Over a Wide Ouptut Power of 180W Jen-Chieh Tsai National Chiao Tung University, Taiwan, Taiwan |
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15:05-15:30 A Chip-Area-Efficient CMOS Low-Dropout Regulator Using Wide-Swing Voltage Buffer with Parabolic Adaptive Biasing for Portable Applications Yonggen Liu, Chenchang Zhan, Lin Cheng, Wing-Hung Ki HKUST, Hong Kong |
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15:30-15:55 A Low-Power and Low-Cost Digitally-Controlled Boost Led Driver IC for Backlights Tak-Jun Oh, Ara Cho, Seok-Lip Ki, In-Chul Hwang Kangwon National University, Korea, South |
Session 10: Oversampling ADCs
Co-Chairs :
Takeshi Yoshida, Hiroshima University
Zhongyuan Chang, Shanghai Belling Co.
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13:50-14:15 A 1.2V 64fJ/Conversion-Step Continuous-Time ΣΔ Modulator Using Asynchronous SAR Quantizer and Digital ΔΣ Truncator Hung-Chieh Tsai, Chi-Lun Lo, Chen-Yen Ho, Yu-Hsin Lin MediaTek Inc., Taiwan |
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14:15-14:40 A 7.5 mW 9 MHz CT ΔΣ Modulator in 65 nm CMOS with 69 dB SNDR and Reduced Sensitivity to Loop Delay Variations Mattias Andersson{2}, Martin Anderson{1}, Lars Sundström{1}, Pietro Andreani{2} {1}Ericsson AB, Sweden; {2}Lund University, Sweden |
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14:40-15:05 A 101 dB DR 1.1 mW Audio ΔΣ Modulator with Direct-Charge-Transfer Adder and Noise Shaping Enhancement Tao Wang{1}, Wei Li{1}, Hirokazu Yoshizawa{2}, Mehmet Aslan{3}, Gabor C. Temes{1} {1}Oregon State University, United States; {2}Saitama Institute of Technology, Japan; {3}Texas Instruments, United States |
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15:05-15:30 A 0.8 V 80.3 dB SNDR Stage-Shared ΔΣ Modulator with Chopper-Embedded Switched-Opamp for Biomedical Application Chuan-Hung Hsiao, Wei-Lin Chen, Chih-Cheng Hsieh National Tsing Hua University, Taiwan |
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15:30-15:55 A 22.4uW 80dB SNDR ΣΔ Modulator with Passive Analog Adder and SAR Quantizer for EMG Application Zhijie Chen{2}, Yang Jiang{2}, Chenyan Cai{2}, He-Gong Wei{2}, Sai-Wen Sin{2}, Seng-Peng U{2}, Zhihua Wang{1}, Rui Paulo Martins{2} {1}Tsinghua University, China; {2}University of Macau, Macau |
Session 11: Milimeter Wave Circuits and Systems
Co-Chairs :
Minoru Fujishima, Hiroshima University
Huei Wang, National Taiwan University
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13:50-14:15 A 245 GHz, 2.6mW/Pixel Antenna-Less CMOS Imager with 0.7fW/Hz05 Nep and 3.5m Backscattered Range Adrian Tang, Hao Wu, Frank Chang UCLA, United States |
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14:15-14:40 A 34.8%-PAE CMOS Transmitter Frontend for 24-GHz FMCW Radar Applications Huan-Sheng Chen, Liang-Hung Lu National Taiwan University, Taiwan |
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14:40-15:05 A 0.7V-to-1.0V 10.1 dBm-to-13.2 dBm 60-GHz Power Amplifier Using Digitally-Assisted LDO Considering HCI Issue Rui Wu, Yuuki Tsukui, Ryo Minami, Kenichi Okada, Akira Matsuzawa Tokyo Institute of Technology, Japan |
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15:05-15:30 A 60 GHz Wideband Active Balun Using Magnitude and Phase Concurrent Correction Technique in 65nm CMOS Shuo-Chun Chou, Fu-Chien Huang, Chorng-Kuang Wang National Taiwan University, Taiwan |
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15:30-15:42 A 60GHz VCO with 25.8% Tuning Range by Switching Return-Path in 65nm CMOS Wei Fei, Hao Yu, Kiat Seng Yeo, Wei Meng Lim Nanyang Technological University, Singapore |
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15:42-15:54 A 60GHz CMOS Rectifier with -27.5dBm Sensitivity for mm-Wave Power Detection Shusuke Kawai, Toshiya Mitomo, Shigehito Saigusa Toshiba, Japan |
Session 12 : Clock Generation and Timing Circuits
Co-Chairs :
Johngsun Kim, Hongik University
Kibune Masaya, Fujitsu Laboratries
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13:50-14:15 A Spread Spectrum Clock Generator Using Phase/Frequency Boosting with a Peak Power Reduction 14.6dB, RMS Jitter 1.45ps and Power 4.8mW/GHz for USB 3.0 Young-Ho Choi, Seong-Hwan Jeon, Byung-Sub Ki, Jae-Yoon Sim, Hong-June Park POSTECH, Korea, South |
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14:15-14:40 A Multi-Phase Multi-Frequency Clock Generator Using Superharmonic Injection Locked Multipath Ring Oscillators As Frequency Dividers Amr Hafez, Ming-Shuan Chen, Ken Yang UCLA, United States |
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14:40-15:05 A High-Resolution Wide-Range Dual-Loop Digital Delay-Locked Loop Using a Hybrid Search Algorithm Jongsun Kim, Sangwoo Han Hongik University, Korea, South |
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15:05-15:30 An All-Digital Phase-Locked Loop with Dynamic Phase Control for Fast Locking Yun-Chen Chuang, Sung-Lin Tsai, Cheng-En Liu, Tsung-Hsien Lin National Taiwan University, Taiwan |
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15:30-15:42 A Cint-Less Type-II PLL with ΔΣ DAC Based Frequency Acquisition and Reduced Quantization Noise Zhuo Zhang, Xican Chen, Woogeun Rhee, Zhihua Wang Tsinghua University, China |
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15:42-15:54 Delay-Line Based Fast-Locking All-Digital Pulsewidth- Control Circuit with Programmable Duty Cycle Jun-Ren Su, Te-Wen Liao, Chung-Chih Hung National Chiao Tung University, Taiwan |
Session 13: SSD Memory and High Frequency Analog
Co-Chairs :
Yasuhiro Sugimoto, Cyuo University
Atsushi Kawasumi, Toshiba
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16:10-16:35 Vset/Reset and Vpgm Generator Without Boosting Dead Time for 3D-ReRAM and NAND Flash Hybrid Solid-State Drives Teruyoshi Hatanaka{2}, Ken Takeuchi{1} {1}Chuo University, Japan; {2}Chuo University, The University of Tokyo, Japan |
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16:35-17:00 An Integrated Variable Positive/Negative Temperature Coefficient Read Reference Generator for MLC PCM/NAND Hybrid 3D SSD Kousuke Miyaji{1}, Koh Johguchi{1}, Kazuhide Higuchi{2}, Ken Takeuchi{1} {1}Chuo University, Japan; {2}University of Tokyo, Japan |
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17:00-17:25 A 5.8GHz Digital Arbitrary Phase-Setting Type II PLL in 65nm CMOS with 2.25deg Resolution Li Li{2}, Mark Ferriss{1}, Michael Flynn{2} {1}IBM T. J. Watson Research Center, United States; {2}University of Michigan, United States |
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17:25-17:50 A 0.5V GFSK 200uW Limiter/Demodulator with Bulk-Driven Technique for Low-IF Bluetooth Chang Ming Lai, Meng Hung Shen, Yi Shuan Wu, Po-Chiun Huang National Tsing Hua university, Taiwan |
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17:50-18:02 Wireless Wafer Probing for on-Chip Analog Voltage Measurement Dae Young Lee, David Wentzloff, John Hayes University of Michigan, United States |
Session 14: Ultra Low-Power Circuits for Emerging Communication System
Co-Chairs :
Jerald Yoo, Masdar Institute of Science and Technology
Seungjun Lee, Ewha Womans University
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16:10-16:35 Photovoltaic-Assisted CMOS Rectifier Circuit for Synergistic Energy Harvesting from Ambient Radio Wave Koji Kotani, Takumi Bando, Yuki Sasaki Tohoku University, Japan |
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16:35-17:00 A 45uW Injection-Locked FSK Wake-Up Receiver for Crystal-Less Wireless Body-Area-Network Joonsung Bae, Hoi-Jun Yoo KAIST, Korea, South |
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17:00-17:25 A 2.4/5.8 GHz 10 µW Wake-Up Receiver with -65/-50 dBm Sensitivity Using Direct Active RF Detection Kuang-Wei Cheng{2}, Xin Liu{1}, Minkyu Je{1} {1}Institute of Microelectronics, Singapore; {2}National Cheng Kung University, Taiwan |
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17:25-17:50 An Asymmetrical QPSK/OOK Transceiver SoC and 15:1 JPEG Encoder IC for Multifunction Wireless Capsule Endoscopy Yuan Gao{2}, San Jeow Cheng{2}, Wei Da Toh{2}, Yuen Sam Kwok{1}, Xi Chen{1}, Wai-Meng Mok{1}, Htun Htun Win{1}, Bin Zhao{2}, Yuanjin Zheng{2}, Sumei Sun{1}, Minkyu Je{2}, Chun-Huat Heng{3} {1}Institute for Infocomm Research, ASTAR, Singapore; {2}Institute of Microelectronics, ASTAR, Singapore; {3}National University of Singapore, Singapore |
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17:50-18:02 A QPSK/16-QAM OFDM-Based 29.1Mbps LINC Transmitter for Body Channel Communication Ping-Yuan Tsai{2}, Jen-Shin Chang{2}, Tsan-Wen Chen{1}, Chen-Yi Lee{2} {1}MediaTek, Taiwan; {2}National Chiao-Tung University, Taiwan |
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18:02-18:14 Continuous-Time High-Precision IR-UWB Ranging-System in 90 nm CMOS Shanthi Sudalaiyandi, Håkon André Hjortland, Tuan-Anh Vu, Øivind Næss, Tor Sverre Lande University of Oslo, Norway |
Session 15 : VCO and PLL
Co-Chairs :
Julien Ryckaert, IMEC
Baoyong Chi, Tsihghhua University
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16:10-16:35 A 0.38 mm2, 10MHz-6.6 GHz Quadrature Frequency Synthesizer Using Fractional-N- Injection-Locked Technique Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa Tokyo Institute of Technology, Japan |
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16:35-17:00 A 0.5-V 5.5-GHz Class-C-VCO-Based PLL with Ultra-Low-Power ILFD in 65 nm CMOS Sho Ikeda, Tatsuya Kamimura, Sangyeop Lee, Norifumi Kanemaru, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu Tokyo Institute of Technology, Japan |
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17:00-17:25 An Energy-Efficient 2.4-GHz PSK/16-QAM Transmitter Chun-Yu Lin{1}, Yao-Hong Liu{2}, Chang-Tsung Fu{3}, Hasnain Lakdawala{3}, Tsung-Hsien Lin{1} {1}National Taiwan University, Taiwan, Taiwan; {2}imec iV Holst Centre, Eindhoven, Netherlands; {3}Intel, United States |
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17:25-17:50 Heterogeneous Coupled Ring Oscillator Arrays for Reduced Phase Noise at Lower Power Consumption Prashant Dubey{2}, Didier Belot{2}, Shouri Chatterjee{1} {1}IIT Delhi, India; {2}STMicroelectronics, France |
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17:50-18:02 A Low Voltage Sub 300uW 2.5GHz Current Reuse VCO Mazhareddin Taghivand{1}, Mohammad Mahdi Ghahramani{2}, Michael Flynn{2} {1}Stanford University, Qualcomm Atheros, United States; {2}University of Michigan, United States |
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18:02-18:14 4 GHz Locking Range and 0.19 pJ Low-Enegy Differential Dual-Modulus 10/11 Prescaler Takeshi Mitsunaka{2}, Masafumi Yamanoue{2}, Kunihiko Iizuka{2}, Minoru Fujishima{1} {1}Hiroshima University, Japan; {2}SHARP, Japan |
Session 16 : Low-Power SoCs and Circuits
Co-Chairs :
Zhiyi Yu, Fudan University
Chenyi Lee, National Chiaotung University
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16:10-16:35 Real-Time Instruction-Cycle-Based Dynamic Voltage Scaling (iDVS) Power Management for Low-Power Digital Signal Processor (DSP) with 53% Energy Savings Shen-Yu Peng National Chiao Tung University, Taiwan |
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16:35-17:00 Ultra-Low-Energy Near-Threshold Biomedical Signal Processor for Versatile Wireless Health Monitoring Xin Liu, Jun Zhou, Xiongfei Liao, Chao Wang, Jianwen Luo, Mohammad Madihian, Minkyu Je Institute of Microelectronics, Singapore |
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17:00-17:25 Performance and Side-Channel Attack Analysis of a Self Synchronous Montgomery Multiplier Processing Element for RSA in 40nm CMOS Benjamin Devlin{2}, Hiroshi Ueki{1}, Shintaro Mori{1}, Shigenori Miyauchi{1}, Makoto Ikeda{2}, Kunihiro Asada{2} {1}Renesas Electronics, Japan; {2}The University of Tokyo, Japan |
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17:25-17:50 A Body Bias Generator Compatible with Cell-Based Design Flow for Within-Die Variability Compensation Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera Kyoto University, Japan |
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17:50-18:15 Self-Test Methodology and Structures for Pre-Bond TSV Testing in 3D-IC System Chao Wang, Jun Zhou, Bin Zhao, Xin Liu, Minkyu Je Institute of Microeletronics, Singapore |